1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a dynamic random access memory (hereinafter, referred to as "DRAM") with a vertically stacked structure wherein a storage capacitor is formed vertically over a junction field effect transistor (hereinafter, referred to as "junction FET") for switching.
2. Description of the Prior Art
Generally, the high integration of a DRAM has been achieved through the development of fabrication equipment and processing technology of semiconductor devices, designing technique, memory cell structure, etc.
However, there have been many problems in developing highly integrated memory device due to the physically imposed limitations consisting in the semiconductor fabrication equipment and semiconductor device itself.
For example, in order to achieve a highly integrated memory device there should be decreased the area for the storage capacitor. However, the conventional memory structure where the storage capacitor and switching transistor are arranged horizontally makes it, not only substantially impossible to reduce the areas for the capacitor and transistor due to the physically imposed limitations, but also requires the fine configuration technique by semiconductor fabrication equipment in order to achieve a highly integrated memory device. Furthermore, the processing technology such as the fine configuration technique is itself very difficult to develop due to the inherent technical limitations.
FIG. 1a illustrates a cross-sectional view of the structure of a conventional DRAM, wherein the switching transistor and storage capacitor are horizontally arranged, and FIG. 1b is an equivalent circuit diagram of FIG. 1a. Referring to FIG. 1a, 40 and 41 respectively represent the drain and source ( or source and drain) of the transistor Q shown in FIG. 1b that are formed on silicon substrate 10. The reference numeral 60 represents the contact between bit line B1 and the diffusion region 40 forming the drain or source. The reference numeral 20 represents an insulating layer for isolating the bit line B1 from word line W13. The word lines W10, W11, . . . and electrode PE are made of polysilicon, and the bit line B1 of aluminum.
In N-channel MOSFET (metal-oxide-semiconductor field effect transistor), the storage capacitor Co is formed between channel 50 and the electrode PE applied with high voltage. In this case, if a pulse voltage is applied to the word line W10, the transistor Q comprising the drain 40 and source 41 connected between the word line W10 and bit line B1 is made conductive, so that the voltage stored in the storage capacitor Co is read out and divided by the bit line B1 and the capacitance of the storage capacitor Co.
More specifically, when the word line W10 is applied with a voltage in order to store data into the conventional DRAM cell, the transistor Q is made conductive by the voltage applied to its gate G, so that the data loaded in the bit line B1 (i.e., voltage of "1" or "0" level) is stored through the conducting transistor Q into the storage capacitor Co.
On the other hand, one electrode of the capacitor Co is the plate electrode applied with a constant reference voltage, while the other electrode that is the storage electrode keeps the voltage stored in the capacitor Co. The voltage of the bit line B1 may be sufficiently stored into the capacitor only provided the voltage of the word line W10 is greater than the voltage of the bit line B1 by the threshold voltage.
In order to read out the data stored in the capacitor, the bit line B1 is precharged with the reference voltage, and the pulse voltage is applied to the word line W10, so that the transistor Q is made conductive so as to deliver the data stored in the capacitor to the bit line. At this time, the bit line undergoes a small voltage variation that ia amplified to readable data.
A typical stacked type conventional DRAM is specifically illustrated in FIG. 1c, wherein the reference numeral 10 represents silicon substrate 10, 40 and 41 respectively the drain and source (or source and drain) of the transistor Q as shown in FIG. 1a, and B1 and W10 respectively the bit line and word lines. The storage capacitor consists of plate electrode PE, storage electrode SE, and dielectric layer DE. This kind of conventional DRAM is disclosed in U.S. Pat. Nos. 4,044,340 issued on Aug. 23, 1977, 3,876,992, 3,979,734, 4,190,466, etc.
In such conventional DRAM's, the areas for the switching transistor and capacitor are great, and the bit line B1 and the plate electrode of the capacitor are separated from each other so that the process for manufacturing the contact, etc. of the memory is complicated, thus making it impossible to achieve a highly integrated memory. Besides, since the transfer transistor consists of a MOS transistor that is lower than a bipolar transistor in the current driving ability, its operating speed is somewhat slower.
Also, U.S. application Ser. No. 07/666,248, as filed by the same applicant on Mar. 8, 1991, discloses a DRAM with vertically stacked structure in which a storage capacitor is formed vertically over a switching transistor. However, the DRAM disclosed in the application uses a bipolar transistor as a switching transistor.
A DRAM with a vertically stacked structure according to the present invention uses a junction FET or a Schottky junction FET as a switching transistor. In details, the present invention is directed to a method for manufacturing the DRAM.